Volume 4 Number 5 (Oct. 2012)
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IJCEE 2012 Vol.4(5): 657-660 ISSN: 1793-8163 DOI: 10.7763/IJCEE.2012.V4.578

An FPGA-Based Controller for High Speed Train System

P. Eh Kan, A. H. Abdul Halim, H. Othman, M. S. Mustafa, and C. Y. Lam
Abstract—The progress of programmable logic devices such as FPGA makes it realize the digital control system without microprocessor recently. A very complex control algorithm can be implemented into FPGA and the calculation time can be dramatically reduced based on parallel processing hardware circuit. In this paper, a design conceptual of original FPGA-based controller for high speed train system is proposed. The Cyclone-II EP2C35F672C6 with EPCS16 16-Mbit serial configuration device is based on SRAM technology and nine embedded array blocks (EABs) are implemented. Based on the simulation result and hardware implementation, the FPGA speed controller has very good performance in controlling high speed train system.

Index Terms—Controller, field programmable gate array (FPGA), hardware, high speed train.

The authors are with the the School of Computer and Communication Engineering, University Malaysia Perlis, 01000 Kangar, Perlis, Malaysia. (e-mail: phaklen@unimap.edu.my, aznor@unimap.edu.my, hazila@unimap.edu.my, sani@unimap.edu.my, cylam@yahoo.com ).

Cite: P. Eh Kan,A. H. Abdul Halim, H. Othman, M. S. Mustafa, and C.Y. Lam, "An FPGA-Based Controller for High Speed Train System," International Journal of Computer and Electrical Engineering vol. 4, no. 5, pp. 657-660, 2012.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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