Volume 3 Number 5 (Oct. 2011)
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IJCEE 2011 Vol.3(5): 645-648 ISSN: 1793-8163
DOI: 10.7763/IJCEE.2011.V3.396

Optimum Repeater Insertion for on-chip Global Interconnects in High Performance Deep Submicron ICs

P. V. Hunagund and A. B. Kalpana

Abstract—This paper addresses the problem of power dissipation during buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is also used to quantify relative importance of various components of the power dissipation for power-optimal solutions for various technology nodes.

Index Terms—Buffer, Dynamic power, Interconnect, Shortcircuit power, Technology nodes.

P. V. Hunagund is with the Department of Applied Electronics, Gulbarga University, Gulbarga, India. e-mail:prabhakar.hunagund@gmail.com.
A. B. Kalpana is with the Electronics and Communication Engineering Department, Bangalore Institute of Technology, Bangalore, India. e-mail:abkalpana@gmail.com.

Cite: P.V.Hunagund and A.B.Kalpana, "Optimum Repeater Insertion for on-chip Global Interconnects in High Performance Deep Submicron ICs," International Journal of Computer and Electrical Engineering vol. 3, no. 5, pp. 645-648, 2011.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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