Volume 2 Number 2 (Apr. 2010)
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IJCEE 2010 Vol.2 (2): 230-234 ISSN: 1793-8163
DOI: 10.7763/IJCEE.2010.V2.142

Delay and Slew Metrics for On-Chip VLSI Interconnect

Rajib Kar, Anuran Chattaraj, Aniruddha Chandra, Ashis K. Mal, and Anup K. Bhattacharjee

Abstract—In deep sub-micrometer (DSM) regime the on-chip interconnect delay is significantly more dominating than the gate delay. Several approaches have been proposed to capture the interconnect delay accurately and efficiently. By interpreting the impulse response of a linear circuit as a Probability Distribution Function (PDF), Elmore first estimated the interconnect delay. Several other approaches like PRIMO, AWE, h-Gamma, WED, D2M etc. have been reported so far, which are shown to be more accurate delay estimation compared to Elmore delay metric. But they suffer from computational complexity when using in the total IC design processes. On the other hand slew rate determines the ability of a device to handle the varying signals. Determination of the slew rate to a good proximity is thus essential for efficient design of high speed CMOS integrated circuits. This in turn estimates the output switching surges in the device. Interconnect slew has become a crucial bottleneck for any high density and high speed VLSI circuits as increased slew results in the increase in delay. Our work presents a closed form formulae for interconnect delay and slew calculation. The proposed metrics are derived by matching circuit moments to the Weibull distribution. This avoids use of complex look-up tables. Experiments validate the effectiveness of our metrics for nets from a real industrial design. We have achieved an average relative error as low as 15% in the delay calculation (compared to the true delay) and 4% in the slew calculation (compared to the true slew value).

Index Terms—Delay calculation, Interconnect, Moment matching, Slew calculation, Weibull Distribution function.

R. Kar, A. Chattaraj, A. Chandra, A. K. Mal, and A. K. Bhattacharjee are with the Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur-713209, WB, India (phone: +91-343-2755514; fax: +91-343-2547375; e-mail: rajibkarece@gmail.com, anuran_nitdgp@yahoo.co.in, aniruddha_chandra@yahoo.co.in, toakmal@gmail.com, akbece12@yahoo.com).

Cite: Rajib Kar, Anuran Chattaraj, Aniruddha Chandra, Ashis K. Mal and Anup K. Bhattacharjee, "Delay and Slew Metrics for On-Chip VLSI Interconnect," International Journal of Computer and Electrical Engineering vol. 2, no. 2, pp. 230-234, 2010.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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