Abstract—Square root is one of the fundamental arithmetic operations used in recent generation processors. In this paper, we present pipelined architecture to implement 8 bit fixed and floating point square root in Field Programmable Gate Array (FPGA) using modified nonrestoring square root algorithm. This algorithm has been optimized by eliminating a number of elements without compromising the precision of the square root and the remainder. It is an improvement over nonrestoring algorithm as it uses only subtract operation and append 01 instead of add operation and append 11. Here the basic building block is Controlled Subtract Multiplex (CSM). By using this module, the algorithm can be designed for any number of input bits. This strategy offers an efficient use of hardware resources. The modified non restoring algorithm is designed using Verilog HDL and implemented on ALTERA cyclone II FPGA. The implementation results show reduced area in terms of logic elements when compared to restoring algorithm.

Index Terms—Controlled subtract multiplex, fixed point, FPGA, nonrestoring, square root, verilog HDL.

The authors are with School of Electronics Engineering, VIT University, Vellore (e-mail:{anujananhe26, gawali.gaurav, shashank.ahire9, ksivasankaran.vlsi}@gmail.com).