Abstract—Efficient implementation of Fast Fourier Transform (FFT) in the hardware paradigm has been a major challenge for design engineers. Twiddle Factor generation and complex multiplication thereafter are the decisive steps of VLSI implementation of FFT. Conventional FFT analyzers call for a dedicated memory bank to store the twiddle factor angles in a predefined order. This storage results in a increased resource utilization which increases with N, the length of the Fourier Transform. This study presents a phase generation scheme that generates the necessary twiddle factor angles with simple hardware logic, depending on the present step and stage of FFT. This relinquishes the use of memory storage elements. Use of CORDIC to carry out complex multiplication further enhances system throughput. The present logic has been synthesized in Spartan 3E FPGA. The timing diagram results match the theoretical analysis and the synthesis report supports minimal hardware resource utilization.

Index Terms—FFT, CORDIC, FPGA, memory-less

Saikat Kumar Shome and Santu Kumar Giri are with Scientist at Electronics & Instrumentation Division of CSIR-CMERI, Durgapur. Pin: 713209. West Bengal (e-mail : saikatkumarshome @gmail.com, saikatkshome@cmeri.res.in, sk_giri@cmeri.res.in)
Smt. Uma Datta is with the Department, Electronics & Instrumentation Division, CSIR-CMERI, Durgapur.(e-mail: uma_datta58@yahoo.in)