Volume 1 Number 1 (Apr. 2009)
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IJCEE 2009 Vol.1 (1): 84-97 ISSN: 1793-8163
DOI: 10.7763/IJCEE.2009.V1.13

Two-dimensional Discrete Wavelet Transform Memory Architectures

Ibrahim Saeed Koko and Herman Agustiawan

Abstract—Until now, the external memory architectures of the two-dimensional discrete wavelet transform (2-D DWT) such as the external RAM and the memory between DWT unit and compression unit, call it, subband memory, which are in need of architecting, have been overlooked in the literature. Since, 2-D DWT memory architectures are equally important as DWT processor architectures commonly covered in the literature, in this paper, two novel VLSI memory architectures for lifting-based 5/3 and 9/7 DWT are proposed. The first proposed memory architecture, the RAM, is read and written by DWT unit only, whereas, the second proposed memory architecture, the subband memory, is written by DWT unit and is read by compression unit.

Index Terms—DWT memory architecture, LL-RAM, subband memory, lifting scheme, and VLSI architecture

The authors are with the Electrical and Electronic Engineering Department, Universiti Teknologi PETRONAS, Perak, Tronoh, Malaysia(emails: kokois12@hotmail.com, herman_agustiawan@petronas.com.my).

Cite: Ibrahim Saeed Koko and Herman Agustiawan, "Two-dimensional Discrete Wavelet Transform Memory Architectures," International Journal of Computer and Electrical Engineering vol. 1, no. 1, pp. 84-97, 2009.

 

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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