Volume 4 Number 3 (Jun. 2012)
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IJCEE 2012 Vol.4(3): 418-422 ISSN: 1793-8163
DOI: 10.7763/IJCEE.2012.V4.525-P157

A Novel FPGA Implementation of Adaptive Rank Order Filter for Image Noise Removal

M. C Hanumantharaju, M. Ravishankar, D. R. Rameshbabu, and S. B. Satish
Abstract—In this paper, a Field Programmable Gate Array (FPGA) implementation of Adaptive Rank Order Filter (AROF) is proposed. AROF is a powerful technique for denoising an image corrupted by salt and pepper noise. This method provides better filtering properties then it is possible with Adaptive Median Filter (AMF). The expansion of the window size in an AMF is based on whether the median is noisy or not. However, this criterion is not an appropriate when the noise density is moderate or high. Further the pixels processed by the AMF are reused in the AMF filtering process. The restored image using this scheme generally degrades the visual quality of an image. The proposed method implements AROF in order to filter images with higher noise densities. The AROF uses median pixel or median computed from noise free pixels in order to replace noisy center pixel. The AROF adapts the window size itself when all pixels within the current window are noisy or when median itself is noisy. The AROF is implemented on Xilinx Vertex XC2VP50-7ff1152 FPGA device. The pipelining and parallel processing techniques have been adopted in order to speed up the filtering process. The experimental results show that the proposed FPGA implementation of AROF has better performance than the AMF, when the noise density is moderate or high. The performance of the proposed algorithm is verified by applying Peak Signal to Noise Ratio (PSNR) and Image Enhance Factor (IEF).

Index Terms—Adaptive rank order filter, adaptive median filter, impulse noise, pipelining, verilog, FPGA.

M. C Hanumantharaju, M. Ravishankar, and D. R Rameshbabu are with the Department of Information Science and Engineering, Dayananda Sagar College of Engineering, Bangalore, India, (e-mail: mchanumantharaju@gmail.com, ravishankarmcn@gmail.com, bobrammysore@gmail.com).
S. B Satish, is with the Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bangalore, India, Pin-560078 (e-mail: satishbhairannawar@gmail.com).

Cite:M. C Hanumantharaju, M. Ravishankar, D. R. Rameshbabu, and S. B. Satish, "A Novel FPGA Implementation of Adaptive Rank Order Filter for Image Noise Removal," International Journal of Computer and Electrical Engineering vol. 4, no. 3, pp. 418-422, 2012.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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