Abstract—This paper presents implementation of a high-speed and low power encryption algorithm with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key encryption algorithm AES(Advanced Encryption Standard), in order to increase the speed and throughput using pipeline technique in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. Also for reducing power consumption using resource sharing, pipelining and signal gating. Such procedure makes AES suitable for fast image encryption. Implementation of a 128-bit AES on FPGA of Altera company has been done and the results are as follow: maximum frequency 475 MHz. power achieved is 301mw in clock frequency 100MHZ. Power is analyzed using Xilinx Xpower analyzer. The time of encrypting in tested image with 32*32 size is 1.25ms.