Volume 4 Number 3 (Jun. 2012)
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IJCEE 2012 Vol.4(3): 367-372 ISSN: 1793-8163 DOI: 10.7763/IJCEE.2012.V4.514

A High Speed and Low Power Image Encryption with 128-Bit AES Algorithm

G. H. Karimian, B. Rashidi, and A. farmani
Abstract—This paper presents implementation of a high-speed and low power encryption algorithm with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key encryption algorithm AES(Advanced Encryption Standard), in order to increase the speed and throughput using pipeline technique in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. Also for reducing power consumption using resource sharing, pipelining and signal gating. Such procedure makes AES suitable for fast image encryption. Implementation of a 128-bit AES on FPGA of Altera company has been done and the results are as follow: maximum frequency 475 MHz. power achieved is 301mw in clock frequency 100MHZ. Power is analyzed using Xilinx Xpower analyzer. The time of encrypting in tested image with 32*32 size is 1.25ms.

Index Terms—Encryption standard(AES), pipelining, signal gating, image encryption, decryption

The authors are with the Department of Electrical and Computer Engineering, University of Tabriz, IRAN (e-mail: karimian@tabrizu.ac.ir, bahram88@ms.tabrizu.ac.ir, ali_farmani88@ms.tabrizu.ac.ir)

Cite: G. H. Karimian, B. Rashidi, and A.farmani, "A High Speed and Low Power Image Encryption with 128-Bit AES Algorithm," International Journal of Computer and Electrical Engineering vol. 4, no. 3, pp. 367-372, 2012.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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