Abstract—Signal reflections due to impedance mismatch at via-interconnect junction is a major signal integrity issue in integrated circuits operating at Giga-Hertz (GHz) frequencies. In this paper, we propose a method to reduce such via induced signal reflections in on-chip global interconnect lines. We show that the impedance matching can be achieved by the inclusion of an appropriate capacitive load at the junction of the on-chip interconnect line and via. Expressions to determine the capacitance value to be added at via-interconnect junction is derived. Simulation results show that the signal refection is reduced to less than -10 dB in the frequency range of 1 GHz to 10 GHz using the proposed method in 65 nm technology. Proposed method is tested for two types of models - (i) Two interconnect layers connected through a single via and (ii) Two interconnect layers connected from layer 6 to layer 1 through five vias.

Index Terms—On-chip interconnects lines, signal reflection,via.

S. Krishna K is with the Department of Electronics and Communication Engineering, St. Joseph Engineering College, Vamanjoor-575028, India(e-mail: ksooryakrishna1@gmail.com).
M. S. Bhat is with the Department of Electronics and Communication Engineering, National Institute of Technology Karnataka, Surathkal, India(e-mail:msbhat@ieee.org).

Cite: Soorya Krishna K and M. S. Bhat, "Impedance Matching in Multi-Layer Interconnect Structures to Minimize Signal Reflections in High Speed Applications," International Journal of Computer and Electrical Engineering vol. 4, no. 3, pp. 345-349, 2012.