Volume 3 Number 2 (Apr. 2011)
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IJCEE 2011 Vol.3(2): 289-296 ISSN: 1793-8163 DOI: 10.7763/IJCEE.2011.V3.329

Network-on-Chip: Power Optimization Architecture Mapping based on Global Interconnection Links

Ei Sayed M. Saad, Medhat H. Awadalla, Sameh A. Salem, and Ahmed M. Mostafa

Abstract—The increasing in communication demands of processing elements (PEs) on Systems on Chips (SoCs) necessitates the existence of Networks-on-chip (NoC) to interconnect the PEs. An important issue in the developing of NoCs is the mapping of the PEs onto the most suitable topology for a specific application. This paper analyzes the system power consumption of the global interconnection links in Networks-on-Chip (NoC)-based systems. Based on this analysis, this paper also proposes a new algorithm to optimize the power consumption on the global interconnection links of NoC-based systems at early design phases. The robustness and reliability of the proposed algorithm is verified in the context of MPEG4 video application. NoC application synthesis and mapping to nine standard topologies are explored. The achieved experimental results show that the proposed optimization algorithm achieve the optimum mapping for all nine topologies in large number of tasks with much less time compared with the exhaustive algorithm.

Index Terms—Architecture mapping, Network-on-Chip, Power optimization, Standard topologies.

Cite: EI Sayed M. Saad, Medhat H.Awadalla, SamehA.Salem, and Ahmed M.Mostafa, "Network-on-Chip: Power Optimization Architecture Mapping based on Global Interconnection Links," International Journal of Computer and Electrical Engineering vol. 3, no. 2, pp. 289-296, 2011.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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