Volume 3 Number 2 (Apr. 2011)
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IJCEE 2011 Vol.3(2): 244-249 ISSN: 1793-8163 DOI: 10.7763/IJCEE.2011.V3.321

Speed and Leakage Power Trade-off in Various SRAM Circuits

Neeraj Kr. Shukla, Shilpi Birla, R. K. Singh and Manisha Pattanaik

Abstract—The growing demand of multimedia rich applications in handled portable devices continuously driving the need for large and high speed embedded Static Random Access Memory (SRAM) to enhance the system performance. Many circuit techniques, e.g. body bias, bit charge recycling etc., have been proposed to expand design margins at low voltage operation while reducing leakage current at standby mode, but the performance is analyzed at the cost of speed and this issue is not addressed widely. Also due to continuous scaling of CMOS, the process variations also affect the performance of SRAMs. This paper presents the analysis of low leakage SRAM along with the speed factor.

Index Terms—Static Random Access Memory, Process Variation, Leakage Current, Low-Voltage Operation.

Cite: Neeraj Kr. Shukla, Shilpi Birla, R.K. Singh and Manisha Pattanaik, "Speed and Leakage Power Trade-off in Various SRAM Circuits," International Journal of Computer and Electrical Engineering vol. 3, no. 2, pp. 244-249, 2011.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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