Volume 2 Number 4 (Aug. 2010)
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IJCEE 2010 Vol.2 (4): 741-746 ISSN: 1793-8163
DOI: 10.7763/IJCEE.2010.V2.221

A Low-Power and High Throughput Reconfigurable Data Integrity Unit for Software Radio

L. Thulasimani and M. Madheswaran

Abstract—Software Radio terminals being able to reconfigure to various radio access systems, will require robust security mechanism to protect the mobile terminals from unauthorized access and to ensure the integrity of internal process involved in reconfiguration when exchanging information with the network. This paper aims to propose an energy efficient reconfigurable hardware architecture which supports data integrity for the secured downloading of software in reconfigurable receivers. Improved SHA-1(SHA-192) algorithm and a reconfigurable hardware design to support different protocols, which uses MD5/SHA 192 algorithm for integrity unit, is proposed. The hash algorithms MD-5, SHA-1, and the unified architecture of MD-5and SHA-192 have been implemented using Verilog, and their hardware utilization on the FPGA device is being compared.

Index Terms—SDR, Reconfigurability, SHA-192, Unified architecture, Hardware utilization.

L.Thulasimani is with the Department of ECE, PSG college of Technology,Coimbatore,INDIA E-mail: lthulasi@gmail.com.
Dr.M.Madheswaran is with Center for Advanced Research, Muthayammal Engineering College, Rasipuram.madheswara.dr@gmail.com

Cite: L.Thulasimani and M.Madheswaran, "A Low-Power and High Throughput Reconfigurable Data Integrity Unit for Software Radio," International Journal of Computer and Electrical Engineering vol. 2, no. 4, pp. 741-746, 2010.

General Information

ISSN: 1793-8163
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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