Volume 2 Number 2 (Apr. 2010)
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IJCEE 2010 Vol.2 (2): 208-211 ISSN: 1793-8163
DOI: 10.7763/IJCEE.2010.V2.138

Modified Architectural Support for Predicate Execution of Instruction level Parallelism

V. Sweta, Ranjit Biswas, and J. B. Singh

Abstract—Utilizing speculative execution alone to extract instruction level parallelism in the presence of branches has performance limitation .The fundamental limitation is that speculation eliminates dependencies between instructions and branches, but does not remove the branches themselves. To overcome this drawback, predicate execution is investigated. Predicate or guarded execution enables a compiler to eliminate branches from the instruction stream. As a result, many of the difficulties introduced by branches can be eliminated. This paper addresses the architectural support required to accomplish predicate execution. The architectural extensions required to provide efficient support for the predicated execution are discussed.

Index Terms—Instruction level parallelism, nullification model, very long instruction word.

V. Sweta is with the Shobhit University (email: sweta_verma@yahoo.com)
Ranjit Biswas is with ITM Gurgaon
J. B. Singh is with Shobhit University

Cite: V. Sweta, Ranjit Biswas, and J. B. Singh, "Modified Architectural Support for Predicate Execution of Instruction level Parallelism," International Journal of Computer and Electrical Engineering vol. 2, no. 2, pp. 208-211, 2010.

General Information

ISSN: 1793-8163
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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