Volume 8 Number 3 (Jun. 2016)
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IJCEE 2016 Vol.8(3): 185-196 ISSN: 1793-8163
DOI: 10.17706/IJCEE.2016.8.3.185-196

Evaluation of Portability and Design Diversity of FabCache

Takahiro Sasaki, Takaki Okamoto, Seiji Miyoshi, Yuki Fukazawa, Toshio Kondo
Abstract—Single-ISA heterogeneous multi-core architecture which consists of diverse superscalar cores is becoming more importantly in the processor architecture. Using a proper superscalar core for characteristic in a program contributes to reduce energy consumption and improve performance. However, designing a heterogeneous multi-core processor requires a large design and verification effort. Therefore, we have proposed FabHetero which generates diverse heterogeneous multi-core processors automatically using FabScalar, FabCache, and FabBus which generate various designs of superscalar core, cache system, and flexible shared bus system, respectively. In our previous work, we estimated the physical design, delay, and power consumption only on a L1 instruction cache of a 32-bit processor. However, almost all modern processor has a L1 data cache, and nowadays there are many 64-bit processors to achieve high-performance computing. This paper shows availability and efficiency of the FabCache by estimating overheads, area, delay, and power consumption, of both instruction cache and data cache systems for both 32-bit and 64-bit processors. FabCache has good portability because bus communication system of generated cache system from FabCache employs AMBA4 protocol that is widely used in various architecture to communicate with other design and its connection logic can be parameterized such as individual bus width. To show an effectiveness and portability of FabCache, this paper applies FabCache to FabScalar-alpha which is a 64-bit processor, and evaluates availability and effectiveness of the generated cache system. According to the evaluation results, the cache systems generated by FabCache works perfectly and the increased area is about 1.7%, delay is 0.1ns, and power is 0.1% compared with hand designed cache system. Evaluation results show that the FabCache can generate reasonable cache system and it has good portability.

Index Terms—Cache generator, design automation, heterogeneous multi-core processor, VLSI design.

The authors are with the Graduate School of Information Technology Engineering, Mie University, Japan. 1577 Kurimamachiya-cho, Tsu city, Mie prefecture, 514-8507, Japan.

Cite:Takahiro Sasaki, Takaki Okamoto, Seiji Miyoshi, Yuki Fukazawa, Toshio Kondo, "Evaluation of Portability and Design Diversity of FabCache," International Journal of Computer and Electrical Engineering vol. 8, no. 3, pp. 185-196, 2016.

General Information

ISSN: 1793-8163
Frequency: Semiyearly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, Engineering & Technology Digital Library, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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