Volume 7 Number 6 (Dec. 2015)
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IJCEE 2015 Vol.7(6): 424-429 ISSN: 1793-8163
DOI: 10.17706/IJCEE.2015.7.6.424-429

Real-Time Evaluation of nMPRA CPU Architecture Based on Multithreaded Execution

Ionel Zagan
Abstract—This paper conducts a thorough study of the schedulability and predictability questions for a custom designed CPU architecture, named Multi Pipeline Register Architecture (nMPRA). The nMPRA CPU implementation uses replication and remapping techniques for the program counter, general purpose registers and pipeline registers, providing predictability and hardware-based isolation for hard real-time threads. We describe the real-time scheduling tests on nMPRA processor architecture, including also a fine-grained multithreading configuration. The present paper highlights several solutions to improve the performance of CPU architectures and to overcome the overhead inconveniences of the Operating Systems.

Index Terms—Fine-grained multithreading, hardware scheduler, pipeline, hard real-time, predictable.

The author is with the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Suceava, Romania.

Cite:Ionel Zagan, "Real-Time Evaluation of nMPRA CPU Architecture Based on Multithreaded Execution," International Journal of Computer and Electrical Engineering vol. 7, no. 6, pp. 424-429, 2015.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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