Volume 6 Number 6 (Dec. 2014)
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IJCEE 2014 Vol.6(6): 509-523 ISSN: 1793-8163
DOI: 10.17706/IJCEE.2014.V6.869

Recent Trends in Low Power VLSI Design

R. Sivakumar, D. Jothi
Abstract—The recent trends in the developments and advancements in the area of low power VLSI Design are surveyed in this paper. Though Low Power is a well established domain, it has undergone lot of developments from transistor sizing, process shrinkage, voltage scaling, clock gating, etc., to adiabatic logic. This paper aims to elaborate on the recent trends in the low power design.

Index Terms—Multi threshold, dynamic voltage and frequency scaling, split level charge recovery logic, efficient charge recovery logic, positive feedback adiabatic logic, pre-resolve and sense adiabatic logic.

The authors are with the Department of ECE, RMK Engineering College, India.

Cite:R. Sivakumar, D. Jothi, "Recent Trends in Low Power VLSI Design," International Journal of Computer and Electrical Engineering vol. 6, no. 6, pp. 509-523, 2014.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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