Volume 1 Number 2 (Jun. 2009)
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IJCEE 2009 Vol.1 (2): 121-125 ISSN: 1793-8163
DOI: 10.7763/IJCEE.2009.V1.19

Hardware Implementation of Low Power Audio Sub word Sorter Unit for High Security Transmission

P. Karthigaikumar and K. Baskaran

Abstract—The security of audio data in high end communication applications like satellites and radars is an issue of concern these days. Designing a processor at the chip level for this requirement is by itself a challenge to VLSI engineers. This paper aims to design a HDL based novel audio subword sorter unit, which is less complex in structure and highly efficient in terms of security. In this paper, we examine the hardware implementation of powerful permutation instruction group (GRP) in low power. This is done at the integrated chip (IC-level) using Verilog HDL and can be implemented in FPGA. To our knowledge this is the first audio subword sorter unit implemented in FPGA.

Index Terms—Cryptography, permutation, audio subword sorter, Network Security, multimedia

1 Assistant Professor (SG) in Electronics and Communication Engineering Department, Karunya University Coimbatore, India.
2Assistant Professor in Computer Science and Engineering Department, Government college of Technology, Coimbatore, India.

Cite: P. Karthigaikumar and K. Baskaran, "Hardware Implementation of Low Power Audio Sub word Sorter Unit for High Security Transmission," International Journal of Computer and Electrical Engineering vol. 1, no. 2, pp. 121-125, 2009.

General Information

ISSN: 1793-8163 (Print)
Abbreviated Title: Int. J. Comput. Electr. Eng.
Frequency: Quarterly
Editor-in-Chief: Prof. Yucong Duan
Abstracting/ Indexing: EI (INSPEC, IET), Ulrich's Periodicals Directory, Google Scholar, EBSCO, ProQuest, and Electronic Journals Library
E-mail: ijcee@iap.org

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